Scalable 5G NR Rate-Matcher and Rate-Dematcher for Efficient Use in FPGA Accelerators

5G new radio supports a variety of new technologies and services, demanding significant improvements in radio access network (RAN) latency, throughput, and flexibility. Disaggregation addresses these challenges by splitting the RAN into network units-central (CU), distributing (DU), and radio (RU), enabling data processing virtualization and implementation on off-the-shelf hardware. However, implementing upper physical layer (PHY) processing on off-the-shelf hardware alone might cause inefficient usage of the server processors. Therefore, acceleration is often needed to offload heavy processing, focusing on low-density parity-check (LDPC) codec as the most compute-intensive task in the PHY. Additionally, LDPC coding is tightly coupled with rate-matching. This paper presents novel hardware architectures of rate-matcher and rate-dematcher, targeting field programmable gate array (FPGA) RAN accelerators. The presented solution's approach to memory organization allows highly parallel operation with efficient hardware resource usage. The architecture is flexible, enabling a selection of various parallelism levels for instant integration with other PHY components, and achieves a throughput of up to 150 Gbps for rate-matching, and up to 35 Gbps for rate-dematching. Both components have been integrated into a Peripheral Component Interconnect Express (PCIe) FPGA acceleration card with an LDPC encoder and decoder. The accelerator performance has been evaluated against OpenAirInterface PHY software. By measuring the acceleration impact on the processor load, it has been shown that with the proposed components, the acceleration efficiency can be increased by an order of magnitude compared to the LDPC-only solution.