A double-modules interlocking triple-node upset-tolerant latch design

In the design of nanoscale latches, multi-node upset (MNU) caused by charge-sharing effects are a major reliability issue. To effectively tolerate MNU under single event effects (SEE), this paper proposes a double-modules interlocking triple-node upset (DMITNU) tolerant latch design. Based on the radiation upset mechanism, utilizing polarity hardened and source isolation techniques, the proposed DMITNU latch can effectively reduce the number of sensitive nodes. The interlocking connection of two basic modules not only cleverly reduces the number of transistors, thereby lowering circuit overhead, but also enhances the MNU radiation tolerance characteristics of the DMITNU latch. Fault injection methods verified the recovery tolerance of the proposed latch. Compared to advanced TNU tolerant latch designs, the proposed DMITNU latch achieved an average improvement of 61 % in the area-power-delay-product (PDAP). Analysis of PVT variations confirmed that the DMITNU latch maintains good stability under harsh environments. Additionally, Monte Carlo (MC) simulations demonstrated that the DMITNU latch has excellent data storage reliability.