A Digitally Reconfigurable Low-Noise Amplifier with Robust Input Impedance for Machine Learning-Based Receiver Optimizations

The surge in demand for wireless connectivity has strongly incentivized advancements in reconfigurable radio frequency (RF) circuits. Although these circuits offer promising opportunities for machine learning (ML)-based optimization when devices are operating in the field, there is still an increasing need to adjust performance and power consumption over wider ranges, especially to dynamically minimize receiver power consumption when possible. In this paper, we present a novel low-noise amplifier (LNA) topology to dynamically scale power and performance to facilitate the realization of real-time ML methods for receiver optimization. This LNA is designed to avoid any significant input impedance matching degradation despite of a wide bias current tuning range to scale the gain, noise figure (NF) and input third-order intermodulation intercept point (IIP3). Simulations of the 2.4 GHz LNA design in 65 nm CMOS technology show its digitally-programmable gain from 17.07 dB to 28.15 dB, NF from 2.56 dB 5.18 dB, and IIP3 from -14.98 dBm to -9.85 dBm, while maintaining consistent input impedance matching with S-11 < -13 dB.