Study for realization of the next generation high density RDL packaging for 2.5D large silicon interposer.

In recent years, with the development of AI processing and deep learning, the demand for GPUs, FPGAs and AI chips has expanded. In order to produce higher performance chips high-speed transmission between different chips is realized by using an interposer, and recently, technology for mounting many chips in an interposer has been developed, as exemplified by Chiplet, and the size of the device is increasing. In the large device, a technology for realizing high-speed communication between chips by embedding a Si chip in a part of an interposer has also been developed. In this paper, we consider the issues and solutions of exposure using a stepper to a large interposer with an embedded Si chip. In particular, we investigated the feasibility of balancing stitching accuracy and MMO accuracy in stepper exposure, and by selecting the optimal exposure sequence, we were able to increase the range in which both stitching and MMO accuracy can be achieved. This study confirmed the conditions and possibility of realizing the next generation large fine patterning interposer.