Hardware-Efficient Implementation of Principal Component Analysis Using High-Level Synthesis

Data whitening is a commonly used technique for preprocessing the raw data to reduce redundancy. The Principal Component Analysis (PCA) algorithm is often employed in the whitening process for dimensionality reduction. Eigenvalue decomposition is a critical and high-time complexity module in PCA. This paper presents an area-efficient implementation of PCA utilizing eigenvalue decomposition with the Lanczos and implicit TriQR algorithm. The hardware is validated on the Pynq-Z1 FPGA using the Xilinx Vivado High-Level Synthesis (HLS) platform, employing loop pipeline optimization. A complete System on Chip solution is developed by interfacing the processor and hardware IP logic unit using the AXI-Lite bus interface. The hardware implementation demonstrates superior resource utilization compared to existing implementations while achieving comparable hardware execution time and frequency, particularly for an input matrix size of 16 x 30.