Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs

被引：0
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作者：
Kahng, Andrew B.
Muddu, Sudhakar
Sarto, Egino
机构：
[1] UCLA Computer Science Dept., 3713 Boelter Hall, Los Angeles, CA 90095-1596, United States
[2] Silicon Graphics, Inc., Mountain View, CA 94039, United States
[3] Silicon Graphics, Inc., 2011 N. Shoreline Blvd., 40L-175, Mountain View, CA 94039, United States
[4] Indian Institute of Technology, Madras, India
[5] University of California, Los Angeles, CA, United States
[6] Intel Corporation, Santa Clara, CA, United States
[7] IBM T. J. Watson Research Center, Yorktown Heights, NY, United States
[8] AT and T Bell Laboratories, Holmdel, NJ, United States
[9] MIPS Technologies, VLSI CAD Group
[10] Silicon Graphics, Inc., United States
[11] Harvard College, United States
[12] University of California, San Diego, CA, United States
[13] Computer Science Faculty, UCLA, United States
[14] ULCA, United States
[15] Cadence Design Systems, Inc., United States
[16] Universidade de Brasilia, Brasilia, Brazil
[17] Stanford University, Stanford, CA, United States
[18] MIPS/Silicon Graphics
[19] Intel
[20] Silicon Graphics
来源：
VLSI Design | / 10卷 / 01期
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页码：21 / 34
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