RTL BEHAVIORAL DESCRIPTION BASED LOGIC DESIGN AID WITH SYNTHESIS CAPABILITY.

被引：0
|
作者：
Nakamura, Yukihiro [1 ]
Oguri, Kiyoshi [1 ]
Nomura, Ryo [1 ]
机构：
[1] NTT, Jpn, NTT, Jpn
来源：
Reports of the Electrical Communication Laboratory | 1988年 / 36卷 / 03期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：319 / 326
相关论文
共 50 条
  • [1] AN RTL BEHAVIORAL DESCRIPTION BASED LOGIC DESIGN AID WITH SYNTHESIS CAPABILITY
    NAKAMURA, Y
    OGURI, K
    NOMURA, R
    REVIEW OF THE ELECTRICAL COMMUNICATIONS LABORATORIES, 1988, 36 (03): : 319 - 326
  • [2] A novel RTL behavioral description based ATPG method
    Yin, ZG
    Min, YH
    Li, XW
    Li, HW
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2003, 18 (03) : 308 - 317
  • [3] A novel RTL behavioral description based ATPG method
    ZhiGang Yin
    YingHua Min
    XiaoWei Li
    HuaWei Li
    Journal of Computer Science and Technology, 2003, 18 : 308 - 317
  • [4] AN INTEGRATED-LOGIC DESIGN ENVIRONMENT BASED ON BEHAVIORAL DESCRIPTION
    NAKAMURA, Y
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (03) : 322 - 336
  • [5] IC Testing by Phase Classification Based on Behavioral Description of RTL
    Huawei Li Yinghua Min and Zhongcheng Li Institute of Computing Technology Chinese Academy of Sciences Beijing China
    湖南大学学报(自然科学版), 2000, (自然科学版) : 104 - 106
  • [6] IC Testing by Phase Classification Based on Behavioral Description of RTL
    Huawei Li
    湖南大学学报(自然科学版), 2000, (S2) : 104 - 106
  • [7] Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
    Princeton Univ, Princeton, United States
    IEEE Trans Comput Aided Des Integr Circuits Syst, 9 (1001-1014):
  • [8] Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
    Ghosh, I
    Raghunathan, A
    Jha, NK
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (09) : 1001 - 1014
  • [9] Method of checking capability model based on description logic
    Dong, Qing-Chao
    Wang, Zhi-Xue
    Chen, Jian
    Zhang, Yi
    Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Systems Engineering and Electronics, 2010, 32 (03): : 533 - 539
  • [10] An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis
    Iwagaki, Tsuyoshi
    Yuasa, Sho
    Ichihara, Hideyuki
    Inoue, Tomoo
    2019 IEEE INTERNATIONAL TEST CONFERENCE IN ASIA (ITC-ASIA 2019), 2019, : 55 - 60
12345