On VLSI decompositions for deBruijn graphs

A very large scale integration (VLSI) decomposition of a graph G is a collection of isomorphic vertex-disjoint subgraphs of G which together span G. Finding an efficient building block for G is corresponding to the design of an efficient single VLSI chip with the property that many identical copies of this chip could be wired together to form a circuit represented by G. To solve this problem, a necessary condition and a sufficient condition for a graph to be a universal building block for deBruijn graphs is given.