Parametric finite element analysis of solder joint reliability of flip chip on board

被引：0
|
作者：
Goh, Teck Joo [1 ]
机构：
[1] Intel Technology Sdn. Bhd., Penang, Malaysia
来源：
Proceedings of the Electronic Packaging Technology Conference, EPTC | 1998年
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摘要：
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页码：57 / 62
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