NOISE CONTROL DURING INTEGRATED CIRCUIT LOGIC CHIP TESTING.

被引:0
|
作者
Anon
机构
来源
| 1646年 / 28期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
INTEGRATED CIRCUIT TESTING
引用
收藏
相关论文
共 50 条
  • [1] INTEGRATED CIRCUIT TESTING.
    Feuerbaum, H.P.
    Metaux corrosion-industries, 1985, 60 (717): : 143 - 152
  • [2] LOW TEMPERATURE LOGIC TESTING.
    Herrell, D.J.
    IBM technical disclosure bulletin, 1983, 26 (05): : 2581 - 2582
  • [3] ECONOMICS OF IN-CIRCUIT TESTING.
    Smith, Tony
    New Electronics, 1979, 12 (23): : 55 - 56
  • [4] Problems in LSI Circuit Testing.
    Wlodarczyk, Janusz
    Meres es automatika, 1984, 32 (08): : 290 - 292
  • [5] On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations
    Ben Dhia, Sonia
    Boyer, Alexandre
    Vrignon, Bertrand
    Deobarro, Mikael
    Thanh Vinh Dinh
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2012, 61 (03) : 696 - 707
  • [6] PHOTOEMISSION SAMPLING TECHNIQUE FOR HIGH-SPEED INTEGRATED-CIRCUIT TESTING.
    Beha, H.
    Seitz, H.
    Blacha, A.
    Clauberg, R.
    Microelectronic Engineering, 1987, 7 (2-4) : 351 - 359
  • [7] MINICOMPUTER SIMULATOR FOR DIGITAL LOGIC TESTING.
    Siwek, Karl
    Electronic Packaging and Production, 1975, 15 (09): : 91 - 92
  • [8] NEW DEVELOPMENTS IN IN-CIRCUIT TESTING.
    Burns, Joseph E.
    1600, (31):
  • [9] COMBINING IN-CIRCUIT AND FUNCTIONAL TESTING.
    Markstein, Howard W.
    Electronic Packaging and Production, 1979, 19 (01): : 75 - 78
  • [10] NEW CHALLENGES FOR IN-CIRCUIT TESTING.
    Ingrams, Kevin
    New Electronics, 1986, 19 (18): : 39 - 40