Interface trap and oxide charge generation under negative bias temperature instability of p -channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

被引：0

作者：

Zhu, Shiyang ^{[1
]}

Nakajima, Anri ^{[1
]}

Ohashi, Takuo ^{[2
]}

Miyake, Hideharu ^{[2
]}

机构：

[1] Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 739-8527, Japan

[2] Elpida Memory, Inc., 7-10 Yoshikawa-kogyo-danchi, Higashi-Hiroshima 739-0198, Japan

来源：

Journal of Applied Physics | 2005年 / 98卷 / 11期

关键词：

Number:; -; Acronym:; MEXT; Sponsor: Ministry of Education; Culture; Sports; Science and Technology;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

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[1] Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics -: art. no. 114504
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JOURNAL OF APPLIED PHYSICS, 2005, 98 (11)
[2] Influence of bulk bias on negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin SiON gate dielectrics
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[3] Bulk and interface trap generation under negative bias temperature instability stress of p-channel metal-oxide-semiconductor field-effect transistors with nitrogen and silicon incorporated HfO2 gate dielectrics
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