SCAN-TESTABLE 6000 GATE ARRAY.

被引:0
|
作者
Berendts, P.A.B. [1 ]
机构
[1] Philips Elcoma, Nijmegen, Neth, Philips Elcoma, Nijmegen, Neth
关键词
D O I
暂无
中图分类号
学科分类号
摘要
9
引用
收藏
页码:377 / 387
相关论文
共 50 条
  • [1] A SCAN-TESTABLE 6000 GATE ARRAY
    BERENDTS, PAB
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 1986, 33 (04) : 377 - 387
  • [2] SCAN PATH MAKES GATE ARRAY TOTALLY TESTABLE
    SMITH, K
    ELECTRONICS, 1983, 56 (15): : 86 - 86
  • [3] ROUTER FOR CMOS GATE ARRAY.
    Zhang Qinhai
    Tang Pushan
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 1985, 6 (06): : 602 - 610
  • [4] DEVELOPMENT OF HYBRID GATE ARRAY.
    Kadono, Shinji
    Suzuki, Yukio
    Torii, Shuichi
    Hitachi Review, 1984, 33 (05): : 261 - 266
  • [5] DIAGONAL LAYOUT OF GATE ARRAY.
    Anon
    IBM technical disclosure bulletin, 1985, 27 (11): : 6727 - 6728
  • [6] UNIVERSAL LOGIC GATE TRANSMISSION GATE ARRAY.
    Zhang, C.
    Electronic Engineering (London), 1985, 57 (706): : 61 - 64
  • [7] INTEGRATED SCHOTTKY LOGIC GATE ARRAY.
    Lau, Stephen Y.
    Electronic components & applications, 1980, 2 (02): : 106 - 114
  • [8] SPEED PERFORMANCE OPTIMIZATION IN ECL GATE ARRAY.
    Kato, Shuichi
    Tatsuki, Makoto
    Kuramitsu, Yohichi
    Horiba, Yasutaka
    Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 1987, 70 (07): : 1 - 11
  • [9] HIGH PERFORMANCE 1200-GATE ISL ARRAY.
    Lau, Stephen Y.
    Wescon Technical Papers, 1979, 23
  • [10] PRECISION SAMPLING GATE USING THE CA3146 ARRAY.
    Harris, R.J.
    Electronic Engineering (London), 1979, 51 (631):