CMOS RADIX-2 SIGNED-DIGIT ADDER BY BINARY CODE REPRESENTATION.

被引：0

作者：

Nakanishi, Tadashi ^{[1
]}

Yamauchi, Hironori ^{[1
]}

Yoshimura, Hiroshi ^{[1
]}

机构：

[1] NTT, Atsugi, Jpn, NTT, Atsugi, Jpn

来源：

Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E | 1986年 / E69卷 / 04期

关键词：

INTEGRATED CIRCUITS - SEMICONDUCTOR DEVICES; MOS;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A binary code representation whih reduces device count for radix-2 signed-digit arithmetic has been proposed and an adder using this binary code has been designed. Delay time of addition is estimated at 5. 5 ns regardless of digit length using 1. 2 mu m CMOS technology.

引用

页码：261 / 263

共 50 条

[1] Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization
Moradian, Hossein
Lee, Jeong-A
Hashmi, Adnan
MICROELECTRONICS RELIABILITY, 2016, 63 : 256 - 266
[2] A low-power FIR filter using combined residue and radix-2 signed-digit representation
Lindahl, A
Bengtsson, L
DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2005, : 42 - 47
[3] CONVERSION FROM SIGNED-DIGIT TO RADIX COMPLEMENT REPRESENTATION
RAJASHEKHARA, TN
NALE, AS
INTERNATIONAL JOURNAL OF ELECTRONICS, 1990, 69 (06) : 717 - 721
[4] Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level
Kliemt, Johannes
Fritscher, Markus
Fey, Dietmar
ARCHITECTURE OF COMPUTING SYSTEMS, ARCS 2024, 2024, 14842 : 237 - 249
[5] Incorporating area-time flexibility to a Binary Signed-Digit adder
Lam, SK
Srikanthan, T
Goyal, N
Tyagi, N
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2002, : 485 - 489
[6] Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation
Timarchi, Somayeh
Navi, Keivan
Kavehei, Omid
2009 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2009, : 97 - +
[7] Design and Implementation of Modified Signed-Digit Adder
Peng, Junjie
Shen, Rong
Jin, Yi
Shen, Yunfu
Luo, Sheng
IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (05) : 1134 - 1143
[8] MULTIPLE-VALUED RADIX-2 SIGNED-DIGIT ARITHMETIC CIRCUITS FOR HIGH-PERFORMANCE VLSI SYSTEMS
KAWAHITO, S
KAMEYAMA, M
HIGUCHI, T
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) : 125 - 131
[9] RADIX-16 SIGNED-DIGIT DIVISION
CARTER, TM
ROBERTSON, JE
IEEE TRANSACTIONS ON COMPUTERS, 1990, 39 (12) : 1424 - 1433
[10] Randomness with respect to the signed-digit representation
Archibald, Margaret
Brattka, Vasco
Heuberger, Clemens
FUNDAMENTA INFORMATICAE, 2008, 83 (1-2) : 1 - 19

← 1 2 3 4 5 →