VLSI architecture for very high resolution scalable video coding using the virtual zerotree

被引：0
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作者：
Ang, Li-minn [1 ]
Cheung, Hon Nin [1 ]
Eshraghian, Kamran [1 ]
机构：
[1] Edith Cowan Univ, Joondalup
来源：
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 1999年
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页码：131 / 140
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