Novel performance analysis approach for network on chip based on analytical router modeling

被引：0

作者：

Lai, Mingche ^{[1
]}

Wang, Zhiying ^{[1
]}

Dai, Kui ^{[1
]}

机构：

[1] College of Computer, National University of Defense Technology, Changsha 410073, China

来源：

Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2009年 / 21卷 / 03期

关键词：

Analytical models - Queueing networks - Network architecture - Network-on-chip - Packet networks - Queueing theory - Routers - Servers;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The highly-efficient analytical performance model for network-on-chip is needed at early stage to guide the design process. Firstly, according to the generalized router architecture, a variety of blockings during the transfer process are analyzed in this paper, and then an analytical router model which uses M/G/1/N queuing system is proposed. Secondly, an NoC performance analysis algorithm is presented, and the formulas for packet delay and saturated throughput are obtained. The comparison between the analysis and simulation results show that the analysis approach with average error of nearly 6.9% achieves a speedup of 200 times. Besides, this approach may also be used to guide application mappings, finding best mapping solutions and exposing performance bottleneck.

引用

页码：339 / 345

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