SystemC system level synthesis method for heterogeneous MPSoC

被引：0
|
作者：
Feng Z.-H. [1 ,2 ]
Chen X. [3 ]
Gao S.-S. [1 ]
机构：
[1] School of Automation, Northwestern Polytechnical Univ.
[2] Beijing Inst. of Computer Technology and Application
[3] Dept. of Electronic Engineering, Tsinghua Univ.
来源：
Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Systems Engineering and Electronics | 2010年 / 32卷 / 11期
关键词：
Architecture; Large scale integrated circuit; System level synthesis (SLS); SystemC;
D O I：
10.3969/j.issn.1001-506X.2010.11.48
中图分类号：
学科分类号：
摘要：
Aiming at the shortcoming of the traditional large scale integrated circuit synthesis method, a novel SystemC electronic system level synthesis (SLS) method is proposed. The heterogeneous multiprocessor system on a chip (MPSoC) hardware architecture which is the target for a system level synthesis system and a SLS synthesis flow are described. The SLS method supports a SystemC untimed model as its design entry and adopts the target MPSoC hardware architecture that has a multiprocessor as the controller and algorithmic IPs as computation accelerators. Furthermore, a system level synthesis integrated development environment (IDE) is implemented, and a MPSoC processor is developed with the IDE. Experimental results show that the proposed synthesis method improves the efficiency of software/hardware mixed MPSoC systems effectively and reduces the time put on the market.
引用
收藏
页码：2484 / 2488
页数：4
相关论文
共 15 条
  • [1] IEEE Standard SystemC language reference manual, (2006)
  • [2] 16, 8, pp. 1070-1073, (2004)
  • [3] Ghenassia F., Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems, (2005)
  • [4] Zimmermann J., Bringmann O., Braun A., Et al., Integration of high-level synthesis in ESL platform modeling by automated generation of protocol adapters, Proc. of the 7th International Conference on Communications, Circuits and Systems, pp. 1149-1154, (2009)
  • [5] Martin G., Gary S., High-level synthesis: Past, present, and future, IEEE Design and Test of Computers, 26, 4, pp. 18-25, (2009)
  • [6] Keinert J., Schlichter T., Falk J., Et al., System CoDesigner - An automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications, Proc. of the 45th Annual Design Automation Conference, pp. 580-585, (2008)
  • [7] Bailey B., Martin G., Piziali A., ESL Design and Verification: A Prescription for Electronic System Level Methodology, (2007)
  • [8] Gerstlauer A., Peng J., Shin D., Et al., Specify-explore-refine (SER): From specification to implementation, Proc. of the 45th annual Design Automation Conference, pp. 586-591, (2008)
  • [9] Martin L., Martin S., Michael G., Et al., Combined system synthesis and communication architecture exploration for MPSoCs, Proc. of the Conference on Design, Automation and Test in Europe, pp. 472-477, (2009)
  • [10] Gruttner K., Oppenheimer F., Nebel W., Et al., SystemC-based modeling, seamless refinement, and synthesis of a JPEG 2000 decoder, Proc. of the Conference on Design, Automation and Test in Europe, pp. 128-133, (2008)
12