Area-selective post-deposition annealing process using flash lamp and Si photoenergy absorber for metal/high-k gate metal-insulator-semiconductor field-effect transistors with NiSi source/drain

被引：0

作者：

Matsuki, Takeo ^{[1
]}

Nishimura, Isamu ^{[1
,2
]}

Akasaka, Yasushi ^{[1
]}

Hayashi, Kiyoshi ^{[1
,3
]}

Noguchi, Masataka ^{[1
,4
]}

Yamashita, Koji ^{[1
,5
]}

Torii, Kazuyoshi ^{[1
,6
]}

Kasai, Naoki ^{[1
,4
]}

Nara, Yasuo ^{[1
]}

机构：

[1] Research Department 1, Semiconductor Leading Edge Technologies, Inc., 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

[2] ROHM Co., Ltd., 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan

[3] Renesas Technology Corp., Marunouchi Bldg., 4-1 Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-6334, Japan

[4] NEC Corp., 7-1 Shiba 5-chome, Minato-ku, Tokyo 108-8001, Japan

[5] Tokyo Electron Ltd., TBS Broadcast Center, 3-6 Akasaka 5-chome, Minato-ku, Tokyo 107-8481, Japan

[6] Hitachi, Ltd., 6-6 Marunouchi 1-chome, Chiyoda-ku, Tokyo 100-8280, Japan

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2006年 / 45卷 / 4 B期

关键词：

We have proposed an area-selective post-deposition annealing (PDA) process that involves a combination of flash lamp annealing and the use of a Si photoenergy absorber (Si-PEA) for metal/high-k gate last metal-insulator- semiconductor field-effect transistors (MISFETs) with NiSi on source/drain (S/D). The process makes it possible to suppress the increase in both the sheet resistance and junction leakage current of NiSi S/D regions. This PDA process also showed optimality for silicide gate electrode formation with silicidation of part of the Si-PEA. It was found that the flash lamp PDA with Si-PEA on nickel-silicide/HfAlOx/SiO2 gate-last MISFETs reduced electron trapping at the gate dielectric and resulted in better PBTI immunity than conventional rapid thermal PDA and flash lamp PDA without Si-PEA. © 2006 The Japan Society of Applied Physics;

D O I：

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学科分类号：

摘要：

Journal article (JA)

引用

页码：2939 / 2944

共 16 条

[1] Area-selective post-deposition annealing process using flash lamp and Si photoenergy absorber for metal/high-k gate metal-insulator-semiconductor field-effect transistors with NiSi source/drain
Matsuki, Takeo
Nishimura, Isamu
Akasaka, Yasushi
Hayashi, Kiyoshi
Noguchi, Masataka
Yamashita, Koji
Torii, Kazuyoshi
Kasai, Naoki
Nara, Yasuo
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B): : 2939 - 2944
[2] Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics
Gottlob, HDB
Mollenhauer, T
Wahlbrink, T
Schmidt, M
Echtermeyer, T
Efavi, JK
Lemme, MC
Kurz, H
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2006, 24 (02): : 710 - 714
[3] Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors
Dai, Chih-Hao
Chang, Ting-Chang
Chu, Ann-Kuo
Kuo, Yuan-Jui
Ho, Szu-Han
Hsieh, Tien-Yu
Lo, Wen-Hung
Chen, Ching-En
Shih, Jou-Miao
Chung, Wan-Lin
Dai, Bai-Shan
Chen, Hua-Mao
Xia, Guangrui
Cheng, Osbert
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APPLIED PHYSICS LETTERS, 2011, 99 (01)
[4] Investigation of Trap Properties in High-k/Metal Gate p-Type Metal-Oxide-Semiconductor Field-Effect Transistors with SiGe Source/Drain Using Random Telegraph Noise Analysis
Wu, San-Lein
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Cheng, Osbert
APPLIED PHYSICS EXPRESS, 2013, 6 (08)
[5] High Electron Mobility Ge n-Channel Metal-Insulator-Semiconductor Field-Effect Transistors Fabricated by the Gate-Last Process with the Solid Source Diffusion Technique
Maeda, Tatsuro
Morita, Yukinori
Takagi, Shinichi
APPLIED PHYSICS EXPRESS, 2010, 3 (06)
[6] Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxide-semiconductor field-effect transistors
Lee, Ju-Wan
Lee, Jong-Ho
APPLIED PHYSICS LETTERS, 2012, 100 (03)
[7] Improved hot carrier reliability characteristics of metal oxide semiconductor field effect transistors with high-k gate dielectric by using high pressure deuterium post metallization annealing
Park, Hokyung
Choi, Rino
Lee, Byoung Hun
Hwang, Hyunsang
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2007, 46 (33-35): : L786 - L788
[8] High Performance Extremely Thin Body InGaAs-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors on Si Substrates with Ni-InGaAs Metal Source/Drain
Kim, SangHyeon
Yokoyama, Masafumi
Taoka, Noriyuki
Iida, Ryo
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Nakane, Ryosho
Urabe, Yuji
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Yasuda, Tetsuji
Yamada, Hisashi
Fukuhara, Noboru
Hata, Masahiko
Takenaka, Mitsuru
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APPLIED PHYSICS EXPRESS, 2011, 4 (11)
[9] Effect of Annealing Process on Trap Properties in High-k/Metal Gate n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors through Low-Frequency Noise and Random Telegraph Noise Characterization
Chiu, Hsu Feng
Wu, San Lein
Chang, Yee Shyi
Chang, Shoou Jinn
Huang, Po Chin
Chen, Jone Fang
Tsai, Shih Chang
Lai, Chien Ming
Hsu, Chia Wei
Cheng, Osbert
JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (04)
[10] Schottky source/drain germanium-based metal-oxide-semiconductor field-effect transistors with self-aligned NiGe/Ge junction and aggressively scaled high-k gate stack
Hosoi, Takuji
Minoura, Yuya
Asahara, Ryohei
Oka, Hiroshi
Shimura, Takayoshi
Watanabe, Heiji
APPLIED PHYSICS LETTERS, 2015, 107 (25)

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