Realization of a digital differential analyzer using CPLDs

The objective is to design and fabricate a wire programmable discrete version of an analog computer known as the digital differential analyzer (DDA) using the binary rate multiplier (BRM) principle without using analog components like operational amplifiers. The bandwidth of the elements can be more than 50kHz. The BRM enables arithmetic-free signal processing. Programming a DDA based on the BRM principle is very similar to the programming of an analog computer due to the structural similarity. The DDA described in this paper uses two wires each at the input and the output ports. One wire is used for carrying the magnitude of the signal in the pulse-rate form and the other wire for the sign of the signal. The paper aims at simulating and synthesizing various modules of a stand-alone-DDA and downloading the synthesized modules on to complex programmable logic devices (CPLDs). Interconnecting various modules in the CPLD can solve differential equations. The results obtained in real time were verified by simulation using (i) ModelSim, (ii) Simulink and (iii) analytical solution of equivalent Z-domain blocks.