Energy-Efficient Dynamic Configurable Datapath Architecture for IoT Devices

This paper introduces a novel RISC-V processor architecture designed for ultra-low-power and energy-efficient applications, particularly for Internet of things (IoT) devices. The architecture enables runtime dynamic reconfiguration of the datapath, allowing efficient balancing between computational performance and power consumption. This is achieved through interchangeable components and clock gating mechanisms, which help the processor adapt to varying workloads. A prototype of the architecture was implemented on a Xilinx Artix 7 field programmable gate array (FPGA). Experimental results show significant improvements in power efficiency and performance. The mini configuration achieves an impressive reduction in power consumption, using only 36% of the baseline power. Meanwhile, the full configuration boosts performance by 8% over the baseline. The flexible and adaptable nature of this architecture makes it highly suitable for a wide range of low-power IoT applications, providing an effective solution to meet the growing demands for energy efficiency in modern IoT devices. © 2024, Posts and Telecom Press Co Ltd. All rights reserved.