Equalization Based Optimization Technique for Group Delay of Cascaded IIR Filter

被引：0
|
作者：
Tong X.-Y. [1 ]
He L.-L. [1 ]
Du H.-M. [1 ]
Dong S.-W. [1 ]
机构：
[1] School of Electronics Engineering, Xi'an University of Posts and Telecommunications, Xi'an, 710121, Shaanxi
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2019年 / 47卷 / 08期
关键词：
All-pass equalizer; Cascaded; Digital filter; Group delay; IIR(Infinite Impulse Response);
D O I：
10.3969/j.issn.0372-2112.2019.08.015
中图分类号：
学科分类号：
摘要：
In order to reduce the output distortion that caused by the non-constant group delay of digital filter, an equalization based optimization technique is proposed, in this paper, for decreasing the variation of group delay in cascaded infinite-impulse response digital filter.By inserting all-pass equalizer behind each stage of the cascaded IIR digital filter, the variation of group delay within the passband range can be reduced, and the output distortion of the digital filter can also be decreased.For the group delay optimization method proposed in this paper, when the 1st and 2nd order equalizers are used for circuit optimization, the variation of group delay is reduced by 28.19% and 49.93% respectively in the passband range of 0~100Hz.Based on the 0.18μm CMOS standard cell library for logic synthesis and layout design, the area of the entire filter circuit IP core layout is 0.1747mm2.Compared with the existing literature methods, this method has a significant effect on group delay optimization, and the power consumption and area are small in circuit implementation, which is very suitable for system-on-chip applications. © 2019, Chinese Institute of Electronics. All right reserved.
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页码：1717 / 1723
页数：6
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