FPGA implementation of PLL-based profile generator

被引：0
|
作者：
Horvat, Robert [1 ]
Jezernik, Karel [1 ]
机构：
[1] Univerza V Mariboru, FERI, Smetanova ulica 17, 2000 Maribor, Slovenia
来源：
Elektrotehniski Vestnik/Electrotechnical Review | 2009年 / 76卷 / 05期
关键词：
Computer hardware description languages - Timing circuits - Digital signal processing - Field programmable gate arrays (FPGA);
D O I：
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学科分类号：
摘要：
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页码：305 / 310
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