Radiation-Hardened by Design Techniques to Mitigate Single-Event Transients in Voltage-Controlled Delay Line

被引：0
|
作者：
Shi Z. [1 ]
Wang B. [1 ]
Zhao Y. [1 ]
Yang B. [1 ]
Lu H. [1 ]
Gao L. [1 ]
Liu W. [1 ]
机构：
[1] Xi'an Microelectronics Technology Institute, Xi'an
来源：
Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology | 2021年 / 41卷 / 12期
关键词：
Delay-locked loop (DLL); Radiation-hardened by design (RHBD); Single-event transient (SET); Voltage-controlled delay line (VCDL);
D O I：
10.15918/j.tbit1001-0645.2100.153
中图分类号：
学科分类号：
摘要：
The voltage-controlled delay line (VCDL) is one of the most sensitive subcircuits to single event (SE) in delay-locked loops (DLLs), which consists of a bias circuit and voltage-controlled delay cells. The sensitivity of VCDL in a DLL to single-event transient (SET) was analyzed based on double exponential current source and 3-D TCAD mixed-mode simulation. According to the difference in the severity of SET response and circuit structure, the bias circuit was hardened by analog redundancy, while a SET detection circuit was proposed for voltage-controlled delay cells. Simulations, making under the condition of 80 MeV•cm2/mg linear energy transfer (LET) values, 1.2 V supply voltage and 1 GHz input reference clock, show the perturbed magnitude of biasing voltages, Vbn and Vbp, can be significantly reduced by 75% and 60%, respectively, completely eliminating missing pulses of output signals compared with the unhardened one. The proposed detection circuit can indicate SET response in voltage-controlled delay cells under different circumstances, improving the reliability of output signals in the DLL. © 2021, Editorial Department of Transaction of Beijing Institute of Technology. All right reserved.
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页码：1314 / 1321
页数：7
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