Customizable FPGA-based Accelerator for Binarized Graph Neural Networks

被引：0
|
作者：
Wang, Ziwei [1 ]
Que, Zhiqiang [1 ]
Luk, Wayne [1 ]
Fan, Hongxiang [1 ]
机构：
[1] Imperial College London, School of Engineering, Dept. of Computing, United Kingdom
来源：
Proceedings - IEEE International Symposium on Circuits and Systems | 2022年 / 2022-May卷
关键词：
Compilation and indexing terms; Copyright 2024 Elsevier Inc;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Data transfer - Digital storage - Graph neural networks - Graphic methods - Integrated circuit design
引用
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页码：1968 / 1972
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