Pistis: A Scheduler to Achieve Ultra Reliability for URLLC Traffic in 5G O-RAN

Supporting ultra reliable low-latency communication (URLLC) is an extremely challenging problem, due to the excessive requirements on reliability and latency. To date, few of the existing research efforts have successfully addressed the ultra reliability problem for URLLC. This article investigates this problem through the design of a URLLC scheduler for industrial automation under the open radio access network (O-RAN) architecture. We cast the URLLC data transmission problem as a resource scheduling problem, where a set of resource blocks (RBs) from a set of O-RAN radio units (O-RUs) must be allocated to a set of user equipments (UEs) for information transmission. The challenge is to find a scheduling solution in each mini-slot (sub millisecond time scale) based on dynamic channel conditions and satisfy the ultra reliability requirement (e.g., 99.9999%, or six-nine). We present Pistis-a novel scheduler design that fully utilizes the three control loops in O-RAN. Pistis exploits channel slow fading and PHY-layer properties to reduce the search space in its design of the near-real time (near-RT) component. It further leverages GPU parallel computing in its design of the real time (RT) component, which takes into account of fast fading in channel dynamics. We implement Pistis on commercial off-the-shelf hardware and demonstrate that Pistis is able to meet the six-nine reliability requirement for 4 O-RUs, 40 RBs, and 40 UEs within 0.5 ms.