Research on Self-Accelerated Establishment Method of Column Bus for Super Large Array CMOS Image Sensor

In the super large array CMOS image sensor (CIS), due to the large parasitic resistance and capacitance on the column bus output by pixel area array, the dominant factor of column bus signal establishment speed is changed, which seriously affects the readout speed. In order to solve the problem, this paper proposes a high-speed readout circuit that can be applied to the very large array of column parallel readout mechanism CIS. Based on the current gain enhancement theory, on the premise of not produce extra bus, by tracking the analog signal establishment process in real time, the change process of the column bus signal is accelerated, self-acceleration is realized in the terminal of the column bus, and the reading speed of the ultra-long column bus is improved by an order of magnitude. The test and experimental results show that after using the method proposed in this paper, for the 47 pF parasitic capacitance and 20 kΩ parasitic resistance generated by the 100 million pixel CIS column bus in the 55 nm process, the rising time of the photoelectric signal from the pixel node to the column level circuit sampling node is shortened from 4 μs to 790 ns, and the falling time decreased from 22.43 μs to 1.17 μs. On the one hand, the frame rate of the multi-million-pixel CMOS image sensor is increased to 100 frames, and the sampling interval time of the relevant double sampling is compressed, so the frequency range of noise suppression is broadened. While realizing low noise and high speed readout, the single-column power consumption is only 6.6 μW. © 2023 Chinese Institute of Electronics. All rights reserved.