A Low-Quiescent-Current Capacitor-less LDO Using an Adaptive PSR Optimization Technique

被引：0
|
作者：
Xu Y. [1 ]
Zhang P.-Y. [1 ]
Li H. [1 ]
Huang K.-T. [2 ]
机构：
[1] The Institute of VLSI Design, Zhejiang University, Zhejiang, Hangzhou
[2] Information Security Center, China Southern Power Grid Research Institute Co.，Ltd., Guangdong, Guangzhou
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2022年 / 50卷 / 07期
关键词：
adaptive supply-ripple cancellation; capacitor-less low-dropout regulator; frequency compensation; low quiescent current; power supply rejection ratio;
D O I：
10.12263/DZXB.20201137
中图分类号：
学科分类号：
摘要：
To improve the power supply rejection ratio(PSR) of capacitor-less low dropout regulator(CL-LDO), this paper proposes an adaptive optimization technique for PSR with low quiescent current. Using push-pull amplifier avoids complex frequency compensation circuits and a bulky external capacitor, thereby reducing the area. To optimize the mid-band PSR, a frequency-dependent compensation current is injected into the gate of the pass transistor. Moreover, a low power dynamic adjustment scheme of the compensation current is adopted to alleviate the impacts of the dropout voltage and load current variations on the optimal PSR improvement. This LDO was designed and fabricated in a 0.11 μm CMOS technology with an active area of 0.026 mm2. The experimental results show that the maximum quiescent current is 55 μA with 0.1-80 mA load current. In the frequency range of 8 kHz to 1 MHz, the maximum PSR improvement is 21-37 dB with different dropout voltages and load currents. © 2022 Chinese Institute of Electronics. All rights reserved.
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页码：1674 / 1683
页数：9
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