Highly reliable pipeline analog-to-digital converter in 0.13 μm standard CMOS process

被引：0

作者：

Zhou Z. ^{[1
,2
]}

Huang S. ^{[1
,2
]}

Dong Y. ^{[1
]}

Lin M. ^{[1
]}

机构：

[1] Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai

[2] University of Chinese Academy of Sciences, Beijing

来源：

Lin, Min (mlin@mail.sim.ac.cn) | 2018年 / National University of Defense Technology卷 / 40期

关键词：

Circuit without sample-and-hold amplifier; Layout reinforcement technology; Pipeline analog-to-digital converter; Total ionizing dose effect;

D O I：

10.11887/j.cn.201806023

中图分类号：

学科分类号：

摘要：

For demanding of high performance analog-to-digital converter for aerospace electronic systems, a 12 bit pipelined analog-to-digital converter with speed of 50 MS/s which can work well in harsh temperature and radiation environment, was presented and implemented with 0.13 μm standard complementary metal Oxide semiconductor process. By employing the circuit without sample-and-hold amplifier, the radiation hardened circuit, and the layout technology, the impact of total ionizing dose effect was significantly alleviated while reducing the power consumption. Test results show that the design achieves a 64 dB signal-to-noise ratio, a 73.5 dB spurious-free dynamic range, maximum 0.22 dB differential nonlinearity within wide temperature range of -55~125 ℃ and survive a total dose of 150 krad(Si). © 2018, NUDT Press. All right reserved.

引用

页码：165 / 170

页数：5

共 15 条

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