The hardware implementation of adaptive non-linear sampling algorithm

In flow-based passive measurement of the Internet, the measurement of flow size and flow volume is a basic requirement. To resolve the contradiction of increasing network link speed and small-sized fast memory chipset, a non-linear sampling algorithm which is named discrete counting (DISCO), was proposed in related research work. In order to meet the need of wire-speed network traffic measurement, DISCO is suggested to be implemented by hardware approaches, such as field-programmable gate array (FPGA). However, DISCO involves complex calculations with high precision, which give rise to a series of challenges in hardware acceleration. To solve the problems, a hardware-friendly refined algorithm was designed, which employs multiple lookup tables and a normalization method. Simulation was conducted to verify the validity of the refined algorithm. An FPGA-based prototype was made. Experiments show that the refined algorithm can achieve wire-speed flow measurement of a 40 Gbit/s link, with small hardware logic resources consumption of FPGA. The average relative error and maximum relative error of the refined DISCO algorithm are close to the original one. © 2016, Editorial Department of Journal of Beijing University of Posts and Telecommunications. All right reserved.