Implementation for RSA cryptography coprocessor

The area and speed of cryptography coprocessor impede the application of public-key cryptography RSA for smart card. A new VLSI architecture of high-radix modular multiplier to compute RSA public-key cryptosystem using our modified Montgomery algorithm is proposed. With TSMC 0.35 μm CMOS technology models, a 1024-bit RSA cryptography coprocessor based on our proposed VLSI architecture is implemented. Its simulation results show that the time to calculate 1024-bit modular multiplication is about 1216 clock cycles and the gate count of the coprocessor is about 38k. At a clock rate of 5MHz it will take about 374ms to encrypt 1024-bit message on average. Compared with previous works our proposed architecture can achieve good performance in chip area and speed, therefore it is well suited to smart cards.