iFail: Predicting end-of-life for future mobile devices

To meet performance and cost goals, device manufacturers are forced to pursue creative new technologies such as FinFETs (3D transistors) and 3D IC integration schemes with bumps, pillars, and through-silicon vias (TSVs). This is where intrinsic semiconductor reliability testing comes into play, enabling designers to find the sweet spot that optimizes both performance and quality while keeping to a quick production schedule. Reliability engineers are also shifting away from the traditional package level reliability (PLR) program toward increasing reliance on wafer level reliability (WLR). For PLR, DUTs are sawn from the wafer, individually packaged, and tested in temperature chambers. WLR uses probe stations and thermal chucks to directly test DUTs on intact wafers.