Power-saving techniques and future design of SPARC64 V/VI

被引：0
|
作者：
Inoue, Aiichiro [1 ,2 ]
机构：
[1] Fujitsu Ltd.
[2] Fuji Photo Film Co., Ltd.
来源：
Fujitsu Scientific and Technical Journal | 2008年 / 44卷 / 01期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
9
引用
收藏
页码：77 / 82
相关论文
共 50 条
  • [1] Power-saving techniques and future design of SPARC64 V/VI
    Inoue, Aiichiro
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2008, 44 (01): : 77 - 83
  • [2] Design development of SPARC64 V microprocessor
    Sakamoto, M
    Katsuno, A
    Inoue, A
    Asakawa, T
    Morita, K
    Motokurumada, T
    Kimura, Y
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (10): : 1955 - 1965
  • [3] Past, Present, and Future of SPARC64 Processors
    Maruyama, Takumi
    Motokurumada, Tsuyoshi
    Morita, Kuniki
    Aoki, Naozumi
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2011, 47 (02): : 130 - 135
  • [4] Validation of Hardware Error Recovery Mechanisms for the SPARC64 V Microprocessor
    Ando, Hisashige
    Kan, Ryuji
    Tosaka, Yoshiharu
    Takahisa, Keiji
    Hatanaka, Kichiji
    2008 IEEE INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS & NETWORKS WITH FTCS & DCC, 2008, : 62 - 69
  • [5] A physical design methodology for 1.3GHz SPARC64 microprocessor
    Ito, N
    Komatsu, H
    Tanamura, Y
    Yamashita, R
    Sugiyama, H
    Sugiyama, Y
    Hamamura, H
    21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 204 - 210
  • [6] Power Reduction Techniques Used in SPARC64 VIIIfx Processor for Fujitsu's Next-Generation Supercomputer
    Kawabe, Yukihito
    Kan, Ryuji
    Yamashita, Hideo
    Okano, Hiroshi
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2012, 48 (02): : 223 - 229
  • [7] PRACTICAL POWER-SAVING TECHNIQUES IN PINELLAS COUNTY
    EDMUNDS, RC
    SOCHA, WM
    PATRICK, RW
    JOURNAL AMERICAN WATER WORKS ASSOCIATION, 1980, 72 (06): : 330 - 337
  • [8] Power-saving design brings DDS flexibility to portables
    Gentile, Ken
    Keip, Jeff
    MICROWAVES & RF, 2008, 47 (03) : 91 - +
  • [9] Design of Smart Power-Saving Architecture for Network on Chip
    Lee, Trong-Yen
    Huang, Chi-Han
    VLSI DESIGN, 2014, Hindawi Limited, 410 Park Avenue, 15th Floor, 287 pmb, New York, NY 10022, United States (2014)
  • [10] Design of Interface ASIC with Power-Saving Switches for Capacitive Accelerometers
    Cai, Juncheng
    Cai, Yongbin
    Li, Xiangyu
    Wang, Shanshan
    Zhang, Xiaowei
    Di, Xinpeng
    Wang, Pengjun
    MICROMACHINES, 2025, 16 (01)
12345