Efficient design and implementation of DFA based pattern matching on hardware

被引：0
|
作者：
Pandey, Aakanksha [1 ]
Khare, Nilay [2 ]
Rasool, Akhtar [2 ]
机构：
[1] M Tech Information Security, Maulana Azad National Institute of Technology, Bhopal, Madhya Pradesh 462003, India
[2] Faculty of Computer Science Engineering, Maulana Azad National Institute of Technology, Bhopal, Madhya Pradesh 462003, India
来源：
International Journal of Computer Science Issues | 2012年 / 9卷 / 02期
关键词：
Clock frequency - Critical networks - Efficient designs - Efficient implementation - Optimized architectures - State minimization algorithms - String matching;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Pattern matching is a crucial task in several critical network services such as intrusion detection. In this paper we present an efficient implementation of the DFA with optimized area and optimized memory by the introduction of state minimization algorithm. By using minimized DFA the clock frequency reduces to 40% of the original and the area also reduces to 30%. This optimized architecture of DFA is simulated and synthesized using VHDL on the Xilinx ISE 12.4.. © 2012 International Journal of Computer Science Issues.
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页码：286 / 290
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