Verification of an SDL specification - A case study

被引：0
|
作者：
Vlaovič, Boštjan [1 ]
Vreze, Aleksander [1 ]
Brezočnik, Zmago [1 ,2 ]
Kapus, Tatjana [1 ]
机构：
[1] University of Maribor, Faculty of Electrical Engineering and Computer Science, Smetanova ulica 17, 2000 Maribor, Slovenia
[2] Laboratory for Microcomputer Systems
来源：
Elektrotehniski Vestnik/Electrotechnical Review | 2005年 / 72卷 / 01期
关键词：
Formal verification - Linear temporal logic (LTL) - Model checking - Specification and description language (SDL) - Spin;
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摘要：
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页码：14 / 21
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