Modified retiming for the timing optimization of high speed logic circuits

被引：0
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作者：
Shen, D. [1 ]
Lin, Z.H. [1 ]
机构：
[1] VLSI Res. Inst., Shanghai Jiaotong Univ., Shanghai 200030, China
来源：
| 2001年 / Shanghai Jiao Tong University卷 / 35期
关键词：
Electron design automatical - Retiming;
D O I：
暂无
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摘要：
(Edited Abstract)
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