A high-capability scattered IP watermarking algorithm in FPGA design

In order to increase watermark amount and watermark security, this paper has analyzed existing FPGA (field programmable gate array) based IP (intellectual property) watermarking techniques and presented a high-capability scattered IP watermarking algorithm in FPGA design. First of all, the algorithm adopts watermark preprocess mechanism for data compression. The mechanism uses compression function for constructing specific linear combination expressions with the encrypted information. The mechanism is not brought to the original design any additional hardware overhead. Secondly, the specific linear combination expressions are then transformed into watermark positions and bit information for being embedded while the watermark is embedded. The bit information are scattered into FPGA circuit by the additional constraint methods. The purpose of this approach is to make it very difficult for illegal user to find the location of the watermark embedding. Finally, through the experimental tests and performance analysis, the algorithm can not only use less embedded bit information amount to mark more watermark information, but also greatly reduce the impact on the system performance because of the embedded watermark information. In addition, through the experimental comparison with existing IP watermarking algorithm in FPGA design, the results show that the proposed algorithm relative to other methods, has a larger capacity of watermark information, a smaller resource overhead, and a better safety performance.