Side-channel attack countermeasure evaluation of cryptographic hardware implementation circuit

The encryption standard, which has been widely used, is computationally secured. It is reported that encryption standard becomes vulnerable against side-channel attacks (SCA) when it was incorporated in hardware. Therefore, various measures against SCA have been proposed. Evaluation and verification of vulnerability against SCA are the most important priority for the measures. This paper proposes a new method for efficient evaluation of SCA measures on design phase of LSI. The proposed method introduces event-modeling simulation and clustering technique in order to achieve highly efficient evaluation. Moreover, the proposed method can detect the vulnerable cells on designing phase of LSI. Experimental results using 018um CMOS standard cell library prove the validity of the proposed method. © 2014 The Institute of Electrical Engineers of Japan.