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- [2] Towards Embedded Systems Formal Verification Translation from SysML into Petri Nets PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2018), 2018, : 420 - 423
- [3] Formal Translation from Reversing Petri Nets to Coloured Petri Nets REVERSIBLE COMPUTATION, 2022, : 172 - 186
- [5] Testable design verification using Petri nets EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2003, : 304 - 311
- [6] Formal verification of PLC-programs generated from signal interpreted Petri nets 2001 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-5: E-SYSTEMS AND E-MAN FOR CYBERNETICS IN CYBERSPACE, 2002, : 2700 - 2705
- [8] Formal Verification of UML State Machine Diagrams Using Petri Nets NETWORKED SYSTEMS, NETYS 2019, 2019, 11704 : 67 - 74
- [10] Design and verification of pipelined circuits with Timed Petri Nets DISCRETE EVENT DYNAMIC SYSTEMS-THEORY AND APPLICATIONS, 2023, 33 (01): : 1 - 24