Novel structure design of the passive UHF RFID tag-chip

A novel structure for the passive UHF RFID tag-chip design is presented for reducing the chip power-consumption and increasing the system operating distance. The tag-chip designed based on the new structure can automatically and synchronously recover the decoding clock out of the data sent from the interrogator and can well generate the backscatter link clock with the values of TRcal and DR specified in the query command that initiates an inventory round. The backscatter link clock frequency has no connection with manufacturing technology and chip working conditions, so it needs no calibration during operation. Since there are no requirements of high frequency sampling-clock or complex frequency-division circuits, which are necessary for conventional structure, the proposed structure is characterized by a smaller circuits scale and lower power-consumption. The chip is designed and fabricated using the TSMC 0. 18μm mixed signal process. Simulation and test results show that the new structure is ten percent smaller in area and thirty percent lower in power comsumption.