A Fast Labeling Algorithm of Connected Components Applicable for Hardware Implementation

被引：2
|
作者：
Zhang G. [1 ]
Xu K. [1 ]
Duan G. [1 ]
Zhao C. [1 ]
Liang F. [1 ]
机构：
[1] School of Electronic and Information Engineering, Xi'an Jiaotong University, Xi'an
来源：
Zhang, Guohe | 2018年 / Xi'an Jiaotong University卷 / 52期
关键词：
Binary image; Connected components labeling; Hardware; Image processing;
D O I：
10.7652/xjtuxb201808015
中图分类号：
学科分类号：
摘要：
A fast labeling algorithm of connected components applicable for hardware implementation is proposed for feature extraction and selection that are commonly used in pattern recognition, computer vision and image processing. First, row scanning is performed to determine consecutive foreground pixels in the same row, i.e., runs, and to record the start and end coordinates of the runs. Then, the run labels and the equivalent run pairs are merged, and temporary values are assigned to these labeled runs according to the connection conditions. Finally, runs of the last row is scanned to determine whether the run of the last row is really over by detecting the corresponding flag bit if it is really finished, and the information of finished region is output, otherwise the next row is scanned. Experiments using different binary images and comparisons with the performance of existing algorithms show that the proposed algorithm has obvious advantages in speed and resource requirements. The average frame rate of image processing speed reaches up to 20 frames/s, and the algorithm requires about 3.45 Mbit on-chip memory resource for an image with a resolution of 2 048×1 536 pixels, which is only 21.9% and 7.6% of the requirements of the block based decision table algorithm and the He algorithm, respectively. © 2018, Editorial Office of Journal of Xi'an Jiaotong University. All right reserved.
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页码：95 / 101
页数：6
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