A Charge Recycling Scheme with Read and Write Assist for Low Power SRAM Design

被引：0
|
作者：
Zhang H. [1 ]
Jia S. [2 ]
Yang J. [1 ]
Wang Y. [2 ]
机构：
[1] Institute of Microelectronics, Peking University, Beijing
[2] Key Laboratory of Microelectronic Devices and Circuits, Peking University, Beijing
来源：
Beijing Daxue Xuebao (Ziran Kexue Ban)/Acta Scientiarum Naturalium Universitatis Pekinensis | 2021年 / 57卷 / 05期
关键词：
Bitline charge cycling; Read and write assist; SRAM;
D O I：
10.13209/j.0479-8023.2021.039
中图分类号：
学科分类号：
摘要：
In order to cut down the dynamic power of static random access memory (SRAM), a bitline charge cycling based read and write assist circuit for SRAM is presented. Compared with the traditional design, the assist circuit saves and reuses the bitline charge which should be directly discharged during read and write operation to reduce bitlines charging power consumption in the next cycle. The SRAM memory is built by the SMIC 14 nm FinFET spice model, and the power supply voltage is 0.8 V. The simulation results show that the power consumption of the proposed SRAM array is reduced by 23%-43% compared with the traditional design, and the SNM and WNM has increased by at least 25% and 647.9% respectively. © 2021 Peking University.
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页码：815 / 822
页数：7
相关论文
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