Design of Quantum Full Adder

被引：0
|
作者：
Chang L. [1 ]
Zhu Y.-X. [1 ]
Jiang H. [1 ]
机构：
[1] School of Information Science and Engineering, Shenyang University of Technology, Shenyang, 110870, Liaoning
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2019年 / 47卷 / 09期
关键词：
Carry look-ahead; Circuit energy consumption; Quantum computer; Quantum cost; Quantum full adder; Reversible logic circuit;
D O I：
10.3969/j.issn.0372-2112.2019.09.007
中图分类号：
学科分类号：
摘要：
Quantum full adder is the basic elements of quantum computers, in order to reduce the energy loss, and cut the construction cost and the difficulty of physical realization, the paper proposes a new type of n-bit quantum full adder which uses 3n CNOT Gates and 2n-1 Toffoli gates to implement n-bit quantum addition and subtraction, adopts the carry look-ahead mode without carry input, and judges the carry of addition and positive and negative sign of subtraction with the highest overflow mark bit that does not participate in the calculation of high and low bit, which does not increase time delay of the circuit and suits for n-bit quantum parallel operation. The simulation operation with random number of 4, 8, 16 and 32 digits verifies the correctness of the full adder separately. The low quantum cost and simple circuit structure of the quantum full adder is helpful to improve the size and integration of integrated circuits. © 2019, Chinese Institute of Electronics. All right reserved.
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页码：1863 / 1867
页数：4
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