共 8 条
- [1] Wang A., Calhoum B.H., Chandrakasam A.P., Sub-threshold Design for Ultra Low-power Systems, pp. 1-3, (2006)
- [2] Siliconsmart User's Guide: Version 2013.06
- [3] Jun J., Song J., Kim C., A near-threshold voltage oriented digital cell library for high-energy efficiency and optimized performance in 65nm CMOS process, IEEE Transactions on Circuits and Systems I, 65, 5, pp. 1567-1580, (2017)
- [4] Wey I.C., Lin P.J., Wu B.C., Et al., Near-threshold-voltage circuit design: The design challenges and chances, International SoC Design Conference (ISOCC), pp. 138-141, (2014)
- [5] Yuan J., Zhang S.M., Shang X.C., Et al., An ultra voltage technique based on foundary standard cell libray, Microelectronics & Computer, 31, 12, pp. 6-9, (2014)
- [6] Jiang J.H., Liang M., Wang L., Et al., An effective timing characterization method for an accuracy-proved VLSI standard cell library, Journal of Semiconductors, 35, 2, pp. 025005-1-025005-5, (2014)
- [7] Library Compiler User's Guide: Version 2016.12
- [8] Charafeddine K., Ouardi F., Fast timing characterization of cells in standard cell library design based on curve fitting, 2017 International Conference on Wireless Technologies, Embedded and Intelligent Systems (WITS), pp. 1-6, (2017)