Reconfigurable Polynomial Multiplication Architecture for Lattice-based Post-quantum Cryptography Algorithms

被引:0
|
作者
Chen T. [1 ]
Li H. [1 ]
Li W. [1 ]
Nan L. [1 ]
Du Y. [1 ]
机构
[1] LA Information Engineering University, Zhengzhou
基金
中国国家自然科学基金;
关键词
Lattice-based post-quantum cryptography; Polynomial multiplication; Preprocesthen-Number Theoretic Transformation (PtNTT); Reconfigurable;
D O I
10.11999/JEIT230284
中图分类号
学科分类号
摘要
Focusing on the current situation that polynomial multiplication parameters in lattice-based cryptography algorithms with different difficult problems and the implementation architecture are not uniform, a reconfigurable architecture based on Preprocess-then-Number Theoretic Transformation (PtNTT) algorithm is proposed. Firstly, the influence of polynomial parameters (number of items, modulus and modulus polynomial) on reconfigurable architecture is integrated by analyzing the characteristics of polynomial multiplication. Secondly, a 4×4 series of parallel convertible arithmetic unit architecture is designed for different terms and modular polynomials, which can meet the scalable design of different bit width k-based number theory transformations. Specifically, a reconfigurable unit that can realize 16-bit modular multiplication and 32-bit multiplication is designed for different modules. In the process of data demand analysis, a multi-bank storage structure satisfying the k-based number theory transformation is designed by constructing a distribution mechanism based on coefficient address generation, bank division and actual and virtual address correspondence logic. Experimental results show that this paper supports the implementation of polynomial multiplication in the four types of algorithms Kyber, Saber, Dilithium and NTRU.The polynomial multiplication operation in the four algorithms can be realized by using a unified architecture compared with the other reconfigurable architectures. A set of polynomial multiplication operations with 256 terms and a modulus of 3329 can be completed at 1.599 ms, consuming 243 clocks on Xilinx Artix-7 FPGA platform. © 2023 Science Press. All rights reserved.
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页码:3380 / 3392
页数:12
相关论文
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