Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory

被引:0
|
作者
Sanuki, Tomoya [1 ]
Horii, Hideto [2 ]
Maeda, Takashi [3 ]
机构
[1] Kioxia Corp, Frontier Technol R&D Inst, Yokaichi, Mie 5120906, Japan
[2] Kioxia Corp, Frontier Technol R&D Inst, Yokohama, Kanagawa 2210022, Japan
[3] Kioxia Corp, Frontier Technol R&D Inst, Yokohama, Kanagawa 2478585, Japan
来源
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2024年 / 12卷
关键词
3D flash memory; thyristor operation; fast-read storage performance; high-speed; SLC; QLC; TECHNOLOGY;
D O I
10.1109/JEDS.2024.3438886
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput.
引用
收藏
页码:710 / 716
页数:7
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