RETRACTED: FPGA based design and implementation of low power dual edge triggered flipflop using dynamic signal driving scheme for memory applications (Retracted article. See vol. 103, 2023)

Power consumption is becoming a massive part of any kind of integrated circuits, and it's a champion rundown of the most basic three problems that guide the most comprehensive development of semiconductors. In an integrated circuit, the clock diffusion framework and flip-flops use a large amount of energy from which they perform and use a large number of internal transitions. Disperses the clock signal, arranged from a common point in each of the parts required for the clock allocation circuit. This range of synchronization is still necessary, but the thought of the story is given to the characteristics of these clock signals. Due to high frequency operation, the clock functions are controlled with clocked transitors. An efficient method to lessen the limit of clock stack is by limiting the quantity of clocked transistors. In this work to propose a propelled system, to embed this clock gating circuit is evaluated by utilizing the Dynamic Signal Driving scheme (DSD) technique. This model is executed in a series of circuits that are used to simulate a defective Electronic Design Automation (EDA) instrument and use it to analyze down power using the Dynamic Signal Driving Program (DSD). The simulation results show that the dynamic power consumption is reduced to a continuous benchmark in circuits. (C) 2020 Elsevier B.V. All rights reserved.