High Reliable and Accurate Stochastic Computing-based Artificial Neural Network Architecture Design

Hardware reliability has emerged as a paramount consideration in the modern Artificial Neural Network (ANN) design in recent years. The un-reliable ANN leads to un-trustable inference results and disasters (e.g., finance system or transportation system crash). To ensure hardware reliability, the common way is to insert some error correctness blocks or fault-tolerant computing blocks, which bring considerable hardware overhead and are improper to the resource-limited edge AI designs. To design hardware-friendly and highly reliable hardware, the Stochastic Computing (SC) method has been proven to be an efficient way to achieve fault-tolerant computing goals. Consequently, many SCbased computing architectures have been introduced recently. However, because of the stochastic number representation, the computing accuracy issue is the design challenge to implement the SC-based computing architecture. To solve this problem, we propose a novel scaling-free adder and input data pre-processing method to achieve a reliable SC-based computing architecture and improve the accuracy of conventional SC-based ANN design. Compared with the traditional ANN design, the proposed SC-based ANN design maintains computing accuracy and enhances the performance by 32% to 55% while facing serious fault injection. In addition, the proposed SC-based ANN architecture reduces 48% to 81% power consumption and 51% to 92% area cost compared with the conventional ANN architecture.