共 16 条
- [1] Evaluation of Variable Bit-Width Units in a RISC-V Processor for Approximate Computing CF '19 - PROCEEDINGS OF THE 16TH ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS, 2019, : 344 - 349
- [3] An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack 34TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT 2021), 2021,
- [7] HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment ASIA CCS'21: PROCEEDINGS OF THE 2021 ACM ASIA CONFERENCE ON COMPUTER AND COMMUNICATIONS SECURITY, 2021, : 187 - 199
- [8] Implementation and Extension of Bit Manipulation Instruction on RISC-V Architecture using FPGA 2020 IEEE 9TH INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT 2020), 2020, : 167 - 172
- [9] Lightweight Secure-Boot Architecture for RISC-V System-on-Chip PROCEEDINGS OF THE 2019 20TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2019, : 216 - 223
- [10] A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip 2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,