FlexBits: A Configurable Lightweight RISC-V Micro-architecture for Flexible Bit-Width Execution

被引:0
|
作者
Xu, Zhiyuan [1 ]
Kang, Xinyu [1 ]
Wang, Xingbo [1 ]
Chen, Bingzhen [1 ]
Ye, Terry Tao [1 ]
机构
[1] Southern Univ Sci & Technol, Shenzhen, Peoples R China
关键词
SIMD; RISC-V; Quantized Neural Networks;
D O I
10.1109/AICAS59952.2024.10595975
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Fixed-point Quantized Neural Networks (QNNs) can significantly reduce computational and bandwidth overhead on energy-efficient edge devices while maintaining comparable accuracy. However, edge devices do not have the flexibility to support multiple-precision fixed point QNN inferences. In this paper, we propose FlexBits, a RISC-V based configurable micro-architecture that supports multiple precisions fix-point QNN inference through Single Instruction Multiple Data (SIMD) custom instruction set. Using FlexBits extension architecture, we further build a VexRiscv compatible CPU, called FlexP that implements the FlexBits instructions with optimized pipeline and logics on FPGA platform. Experimental results demonstrate substantial improvements for convolution operations quantized to 2, 4, 8, and 16 bits, with average speedups of 20.8x, 7.6x, 3.0x, and 1.7x, respectively, as compared to the baseline processors without the extended instructions. In the inference task of 8-bit quantized MobileNetV1, the end-to-end inference speedup is 1.57x, achieving inference performance comparable to ARM Cortex-M4.
引用
收藏
页码:287 / 291
页数:5
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