Integration of Shift-Left Updates into Logic Synthesis and Macro Placement

被引:0
|
作者
Guo, Xinfei [1 ,2 ]
Zhao, Xiaotian [1 ]
Zhu, Linyu [1 ]
机构
[1] Shanghai Jiao Tong Univ, Univ Michigan Shanghai Jiao Tong Univ Joint Inst, Shanghai, Peoples R China
[2] Fudan Univ, SKLICS, Shanghai, Peoples R China
来源
CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC | 2024年
基金
国家重点研发计划;
关键词
D O I
10.1109/CSTIC61820.2024.10531906
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
The shift left methodology in Electronic Design Automation (EDA) presents a pathway for the creation of digital twins, facilitating the transition of subsequent physically-aware design processes into virtual environments. This shift empowers designers to establish stronger correlations and optimize their designs more effectively. However, it is crucial to identify when and how to implement this shift, especially considering the challenges in replicating subsequent behaviors accurately. Given that synthesis marks the initiation of the entire physical implementation phase, and macro placement serves as the starting point for intensive automated placement, we have pinpointed opportunities to introduce shift left updates to these critical stages. By incorporating a physically aware timing model into logic synthesis, we have significantly enhanced design quality in terms of timing. Additionally, by preemptively considering macro-cell connections as a co-optimization target, improvements have been observed in routing length and congestion, leading to more efficient designs.
引用
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页数:3
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