A Broadband 22 nm FDSOI D-Band Power Amplifier with Dynamic Back Gate Bias Gain-Linearization Achieving 9.6% PAE at 8.7 dBm OP1dB and 3.7% at 6 dB Back-off

This work presents a high-efficiency four-stage D-band power amplifier (PA) in a 22nm FDSOI technology. The PA incorporates a dynamic biasing scheme that utilizes the SOI transistor's back-gate terminal to optimize the DC power consumption of each stage based on the corresponding input envelope power level. This dynamic bias control significantly improves the linearity and efficiency in the linear and power compression range. The work describes the associated power detectors and the design of a stacked FET output stage used for output power enhancement. Low-k stacked transformers are employed as interstage matching elements to broaden the bandwidth. The PA achieves 24.5 dB gain, covering a 3-dB bandwidth of 36 GHz centered at 138 GHz. Saturated output power and OP1dB of 10.8dBm and 8.6dBm at nominal supply voltage of 1.6/0.8V is reached while only occupying a core area of 0.045 mm(2). Achieving 9.6% PAE at OP1dB and 3.7% at 6-dB power back-off, the PA demonstrates significant improvement compared to reported D-band PAs in CMOS technology.