Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM

There has been an increasing need for wide-bandwidth and high-density DRAMs. Wide-bandwidth DRAMs, in which DRAM dies are stacked using a through-silicon via (TSV), have a limitation on the number of connected chips due to the wide pitch of TSV. A high-density 4F(2) DRAM cell using an indium-gallium-zinc oxide FET has been reported. However, no reports have been made so far on subarray prototypes. To address these issues, we introduce a 1-Mbit three-dimensional (3D) oxide semiconductor (OS) DRAM formed using heterogeneous OSFETs monolithically stacked on a Si CMOS. The heterogeneous OSFETs comprise one planar FET layer and two upper vertical channel FET (VFET) layers. The planar FET and Si CMOS are used for the first and second sense amplifiers, respectively. The VFET is used for a one transistor-one capacitor ( lTlC) 4F2 3D OS DRAM cell. The off-state currents of the planar FET and VFET are 1.6 x 10(-21) A/FET and 1.5 x 10(-22) A/cell, respectively. The 1-Mbit 3D OS DRAM includes one 60-nm planar FET and two 40-nm VFETs as heterogeneous OSFETs and a 130-nm Si CMOS. The proposed 3D OS DRAM operates with read and write times of 60 and 50 ns, respectively. The initial error is reduced by 92.7% after performing threshold voltage compensation on the read FETs. Over 99% of the data are retained after 1 h at 85 degrees C without refresh.